Tilera announced today a monster CPU that utilizes a "tile" achitecture to enable 64 CPU cores to be placed on a single chip, with all the high speed I/O, eliminating the need for a northbridge and southbridge chips, vastly cutting power consumption and board real estate. The best part is it runs SMP Linux kernel 2.6 and can be optimized with almost all existing C/C++ code.
From the Tilera web site:
The TILE64™ family of multicore processors delivers immense compute performance to drive the latest generation of embedded applications. This revolutionary processor features 64 identical processor cores (tiles) interconnected with Tilera's iMesh™ on-chip network. Each tile is a complete full-featured processor, including integrated L1 & L2 cache and a non-blocking switch that connects the tile into the mesh. This means that each tile can independently run a full operating system, or multiple tiles taken together can run a multi-processing operating system like SMP Linux.
With a standard ANSI C programming environment, developers can leverage their existing software investment as well as utilize the vast body of Open Source code available. Tiles can be grouped into clusters to apply the appropriate amount of horsepower to each application. Since multiple operating system instances can be run on the TILE64™ simultaneously, it can replace multiple CPU subsystems for both the data plane and control plane.
• 8 X 8 grid of identical, general purpose processor cores (tiles)
• 3-way VLIW pipeline for instruction level parallelism
• 5 Mbytes of on-chip Cache
• 192 billion operations per second (32-bit)
• 27 Tbps of on-chip mesh interconnect
• Up to 50 Gbps of I/O bandwidth
I/O Specs are:
• Four DDR2 memory controllers with optional ECC
• Two 10GbE XAUI MAC/PHY interfaces
• Two 4-lane 10Gbps PCI-e MAC/PHY interfaces
• Two GbE MAC interfaces
• Flexible I/O interface